1
wire  variable_rise;
2
reg    variable_r1;
3
reg    variable_r2;
4

5
assign variable_rise = ~variable_r2 & variable_r1;  //检测上升沿
6

7
always @(posedge clk_50m or negedge rst_n) begin
8
  if(!rst_n) begin
9
    variable_r1 <= 1'b1;
10
    variable_r2 <= 1'b1;
11
  end
12
  else begin
13
    variable_r1 <= variable;
14
    variable_r2 <= variable_r1;
15
  end
16
end

1
wire  variable_fall;
2
reg    variable_r1;
3
reg    variable_r2;
4

5
assign variable_fall = variable_r2 & ~variable_r1;  //检测下降沿
6

7
always @(posedge clk_50m or negedge rst_n) begin
8
  if(!rst_n) begin
9
    variable_r1 <= 1'b0;
10
    variable_r2 <= 1'b0;
11
  end
12
  else begin
13
    variable_r1 <= variable;
14
    variable_r2 <= variable_r1;
15
  end
16
end

1
module  led
2
#(  parameter N = 10,
3
  parameter TIMEOUT = 32'd5_000_000)
4
 (  input                clk,
5
  input                rst_n,
6
  output  reg  [N-1 : 0]  led
7
);
8

9
reg  [31:0]  cnt;  //确定亮灯的时间间隔
10
always @(posedge clk or negedge rst_n) begin
11
  if(!rst_n)
12
    cnt <= 'h0;
13
  else if(cnt == TIMEOUT - 1'b1)
14
    cnt <= 'h0;
15
  else
16
    cnt <= cnt + 1'b1;
17
end
18

19
always @(posedge clk or negedge rst_n) begin
20
  if(!rst_n)
21
    led <= 'b1;
22
  else if(cnt == TIMEOUT - 1'b1)
23
    if(led[N-1] == 1'b1)
24
      led <= 'b1;
25
    else
26
      led <= led << 1;
27
  else
28
    led <= led;
29
end
30

31
endmodule

1
module  decoder_4_16(
2
  input          enable,
3
  input    [3:0]    in,
4
  output    [15:0]    out
5
);
6

7
  wire    [3:0]    high_d;
8
  wire    [3:0]    low_d;
9

10
  assign high_d[3] = ( in[3]) & ( in[2]) & enable;
11
  assign high_d[2] = ( in[3]) & (~in[2]) & enable;
12
  assign high_d[1] = (~in[3]) & ( in[2]) & enable;
13
  assign high_d[0] = (~in[3]) & (~in[2]) & enable;
14

15
  assign low_d[3]  = ( in[1]) & ( in[0]);
16
  assign low_d[2]  = ( in[1]) & (~in[0]);
17
  assign low_d[1]  = (~in[1]) & ( in[0]);
18
  assign low_d[0]  = (~in[1]) & (~in[0]);
19

20
  assign out[15] = high_d[3] & low_d[3];
21
  assign out[14] = high_d[3] & low_d[2];
22
  assign out[13] = high_d[3] & low_d[1];
23
  assign out[12] = high_d[3] & low_d[0];
24
  assign out[11] = high_d[2] & low_d[3];
25
  assign out[10] = high_d[2] & low_d[2];
26
  assign out[9]  = high_d[2] & low_d[1];
27
  assign out[8]  = high_d[2] & low_d[0];
28
  assign out[7]  = high_d[1] & low_d[3];
29
  assign out[6]  = high_d[1] & low_d[2];
30
  assign out[5]  = high_d[1] & low_d[1];
31
  assign out[4]  = high_d[1] & low_d[0];
32
  assign out[3]  = high_d[0] & low_d[3];
33
  assign out[2]  = high_d[0] & low_d[2];
34
  assign out[1]  = high_d[0] & low_d[1];
35
  assign out[0]  = high_d[0] & low_d[0];
36

37
endmodule