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module  divide_N
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#(parameter DIV = 7)
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(    input    clk_in,
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    input    rst_n,
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    output  clk_out
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);
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reg  clk_pos;
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reg  clk_neg;
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reg  [15:0]  cnt_pos;
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reg  [15:0]  cnt_neg;
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always@(posedge clk_in or negedge rst_n) begin
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  if(!rst_n)
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    cnt_pos <= 1'b0;
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  else if(cnt_pos == (DIV - 1'b1))
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    cnt_pos <= 1'b0;
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  else
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    cnt_pos <= cnt_pos + 1'b1;
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end
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always@(posedge clk_in or negedge rst_n) begin
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  if(!rst_n)
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    clk_pos <= 1'b1;
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  else if(cnt_pos == ((DIV - 1'b1)/2))
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    clk_pos <= 1'b0;
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  else if(cnt_pos == 1'b0)
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    clk_pos <= 1'b1;
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  else
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    clk_pos <= clk_pos;
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end
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always@(negedge clk_in or negedge rst_n) begin
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  if(!rst_n)
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    cnt_neg <= 1'b0;
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  else if(cnt_neg == (DIV - 1'b1))
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    cnt_neg <= 1'b0;
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  else
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    cnt_neg <= cnt_neg + 1'b1;
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end
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always@(negedge clk_in or negedge rst_n) begin
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  if(!rst_n)
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    clk_neg <= 1'b1;
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  else if(cnt_neg == ((DIV - 1'b1)/2))
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    clk_neg <= 1'b0;
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  else if(cnt_neg == 1'b0)
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    clk_neg <= 1'b1;
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  else
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    clk_neg <= clk_neg;
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end
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assign  clk_out = clk_pos | clk_neg;
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endmodule

1
`timescale 1ns/1ns
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`define CLK50M_PERIOD 20
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module  divide_N_tb;
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  reg  clk;
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  reg  rst_n;
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  wire  clk_out;
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parameter  DIV = 7;
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initial clk = 1'b1;
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always #(`CLK50M_PERIOD/2) clk = ~clk;
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initial begin
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  rst_n = 0;
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  #(`CLK50M_PERIOD * 20 + 1)
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  rst_n = 1;
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  #5000;
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  $stop;
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end
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divide_N
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#(  .DIV(DIV)
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  )divide_N
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(  .clk_in(clk),
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  .rst_n(rst_n),
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  .clk_out(clk_out)
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);
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endmodule